Revisiting the Perceptron Predictor

The perceptron branch predictor has been recently proposed by Jiménez and Lin as an alternative to conventional branch predictors. In this paper, we build upon this original proposal in three directions. First, we show that the potential accuracy that can be achieved by perceptron-like predictors was largely underestimated. The accuracy of the redundant history skewed perceptron predictor (RHSP) we are proposing is significantly higher than the one of the original perceptron predictor. The RHSP predictor combines pseudo-tagging, i.e., using address bits as part of the input vectors, use of a redundant representation of the history (4 counters per history bit) and skewing, i.e., use of split tables indexed with different hashing functions. Second, we drastically simplify the hardware logic needed for prediction computation and predictor update. We introduce the MAC representation (for Multiply-Add Contribution) for the perceptron counters in the RHSP predictor. This new representation allows to reduce the width of the multiply-accumulation tree in the RHSP predictor by a factor 16. The width of the represented values can also be reduced from 8 bits to 6 bits without significant accuracy loss on the MAC-RHSP predictor. Response time is a major obstacle for the use of perceptron predictors in real processors. The third contribution of this paper is to propose an ahead pipelined MAC-RHSP predictor. Even assuming that the prediction is initiated 10-block ahead the instruction flow, the accuracy of the ahead pipelined MAC-RHSP predictor remains in the same range as the one of the hypothetical 1-cycle MAC-RHSP predictor. Moreover the volume of information to be checkpointed with each fetch block to allow smooth restart with no extra misprediction penalty remains limited.